The subject matter of the present application is related to that in co-pending U.S. patent application Ser. No. 09/901,899 entitled xe2x80x9cSYSTEM AND METHOD FOR CALIBRATING ISOLATED ANALOG-TO-DIGITAL CONVERTERSxe2x80x9d and co-pending U.S. patent application Ser. No. 09/834,630 entitled xe2x80x9cCAPACITATIVELY COUPLED REFERENCES FOR ISOLATED ANALOG-TO-DIGITAL CONVERTER SYSTEMSxe2x80x9d, both of which are incorporated herein by reference.
The present invention relates to isolation for analog-to-digital converter systems, and more particularly to full duplex communications channels for isolated analog-to-digital converter systems.
FIG. 1 is a block diagram of a measurement system 9 of the Prior Art. Such measurement systems may be used to measure various analog parameters in environments where voltage isolation is required. For example, in power monitoring systems (e.g., residential power metering) a measurement device (front end) may be measuring power at line voltage (e.g., 220 Volts) and some form of isolation may be required to protect the user and processor (back end) which may be at a much lower potential. Similarly, in medical systems, voltage isolation may be required as a fail-safe to prevent a patient from being electrocuted due to potential differences between various medical monitoring devices.
Referring to FIG. 1, measurement system 9 may include a digital signal processor (DSP) 11, link chip 12, capacitor C113, analog-to-digital converter (ADC) and link chip 15, and a sensor 16. Sensor 16 may comprise any one of a number of known analog sensors for measuring a particular parameter (e.g., temperature, pressure, voltage, amperage, power consumption, or the like).
Analog-to-digital converter (ADC) and link chip 15 may convert the analog output of sensor 16 to a digital value (typically a onebit data stream) and outputs this data stream to a digital signal processor (DSP) 11 via link chip 12 and isolation capacitor 13. In addition to digital data values transmitted from analog-to-digital converter (ADC) and link chip 15 to digital signal processor (DSP) 11, other signals may need to be exchanged between the two chips. For example, clock signals and control signals (including calibration signals or voltage levels) may be transmitted from digital signal processor (DSP) 11 to analog-to-digital converter (ADC) through link chip 15. In addition, digital signal processor (DSP) 11 may need to provide power supply voltage to analog-to-digital converter through link chip 15. In the Prior Art, additional signal lines may be required for such additional signals, increasing the complexity and cost of the device.
As noted above, in many applications, such as power metering, it may be necessary to isolate analog-to-digital converter (ADC) from link chip 15 and digital signal processor (DSP) 11 due to differences in voltage potential. To isolate the voltage potential between analog-to-digital converter and link chip 15 and digital signal processor (DSP) 11, an isolation capacitor 13 may be employed.
Such isolation practices, however, may create problems when attempting to communicate from digital signal processor (DSP) 11 and link chip 15 and analog-to-digital converter (ADC) and vice versa. With a small capacitance value C1 for capacitor 13, the use of a digital tri-state gate in link chip 12 and link chip portion of analog-to-digital converter (ADC) and link chip 15 for transmitting data is disadvantageous due to voltage division losses. Nevertheless, using a digital tri-state gate is advantageous for transmitter energy, clock, and command sources, as well as for receiver systems. However, when a transmitter produces a square wave according to a Manchester encoded clock and control scheme, for example, isolation capacitor 13 may block the square wave from the transmitting transformer.
FIG. 2 is a block diagram of another embodiment of a measurement system 19 of the Prior Art. Measurement system 19 includes a digital application specific integrated circuit (ASIC) or programmable logic device (PLD) 21 such as a digital signal processor and link chip, a resistor 22, capacitor 23, transformer 24, analog-to-digital converter (ADC) 25 and capacitor 26.
ASIC or PLD 21 may include a transmitter 27 and receiver 29 coupled to each other through switch 28. Data may be selectively transmitted and received over the connection between ASIC or PLD 21 and ADC 25. In addition, ASIC or PLD 21 may provide power to ADC 25 through this same link.
ADC 25 may include a diode 30 and a rectifier 31. Signals from secondary winding 33 of transformer 24 may be rectified by rectifier 31 and diode 30 to produce a voltage a capacitor 26 which in turn is the power supply for ADC 25.
As in the embodiment of FIG. 1, transmitter 27 may transmit to primary winding 32 of transformer 24 a square wave which may be partially blocked or distorted by capacitor 23 from transformer 24. ADC 25 may detect a pause during the tristate operation and takes over the data link, sending data and status back to receiver 29. During this take-over period, however, voltage at power supply 26 may droop significantly if many bits are transmitted, and full logic levels may not re-establish themselves.
The present invention provides an isolated analog-to-digital converter system including an analog-to-digital converter subsystem for converting an analog signal to a digital data stream. A microcontroller subsystem provides power, clock signals, and data signals as a single combined signal for the analog-to-digital converter, the single combined signal comprising a pulse train having a nominal frequency and having data pulse width modulated thereon. An isolation subsystem electrically isolates the analog-to-digital converter subsystem from the microcontroller subsystem.
The isolation subsystem includes a first transformer, coupled to the microcontroller subsystem, which receives the single combined signal as a differential input signal. A full-wave rectifier, coupled to the first transformer, rectifies the differential input signal to produce at least one power supply voltage for the analog-to-digital converter subsystem. A voltage divider, coupled to the first transformer receives the differential input signal and outputs the combined pulse width data signals and clock signals to the analog-to-digital converter subsystem at a reduced amplitude.
The full-wave rectifier includes a first diode having an anode coupled to one leg of the first transformer and a cathode capacitively coupled to another leg of the first transformer. The first diode produces a first supply voltage at its cathode. A second diode has a cathode coupled to the one leg of the first transformer and an anode capacitively coupled to the another leg of the first transformer. The second diode produces a second supply voltage at its anode.
In addition, a second transformer having one leg coupled to the analog-to-digital converter subsystem receives the digital data stream from the analog-to-digital converter synchronous with the clock signals and outputs the digital data stream to the microcontroller subsystem. The clock signal sent to the ADC allows the return data to be sent synchronously, greatly simplifying the return data path configuration.